Mask Layout Engineer

Acceler8 Talent is recruiting for an early-stage AI hardware company developing custom inference silicon. The Mask Layout Engineer will translate transistor-level schematics into manufacturable custom layouts and own custom cells and blocks through full-chip integration, physical verification, and tape-out sign-off.

Responsibilities:

• This role will work directly with the CTO and circuit designer, a former CPU design lead on Intel’s first Pentium, to translate transistor-level schematics into dense, manufacturable custom layouts
• You will own custom cells and blocks through full-chip integration, physical verification and tape-out sign-off
• Translating transistor-level schematics into dense custom layouts
• Designing tight-pitch cells, bitcells and repeated circuit arrays
• Owning block assembly, full-chip integration and physical sign-off
• Closing DRC, LVS, antenna and density issues using Calibre or IC Validator
• Optimizing matching, symmetry and parasitics while providing schematic feedback
• Automating useful layout tasks through SKILL scripting

Requirements:

• Delivered several custom IC layout tape-outs, including top-level sign-off
• Strong Cadence Virtuoso and Calibre or IC Validator experience
• Designed dense custom cells, bitcells or memory arrays
• Worked at 28nm or a comparable process node
• Independently resolved difficult layout and verification issues
• Experience with complex ESD structures, antenna closure, dummy fill and SKILL automation