Key skills
Communication
About this role
- 5+ years of hands-on RTL design experience (SystemVerilog / Verilog)
- Strong understanding of micro-architecture and RTL implementation from specs
- Experience in DSP hardware implementation (filtering, FFT, etc.)
- Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verification
- Experience with synthesis, linting, simulation, and STA tools
- Understanding of DFT concepts (scan, BIST)
- Strong debugging and problem-solving skills
- Good communication and ability to work in cross-functional teams