Own power-delivery design end to end, from on-die power grids to package and PCB PDN design and analysis.
Lead advanced packaging architecture decisions for 2.5D/3D stacking, multi-chiplet integration, and interposer/substrate co-design.
Perform SI/PI verification and sign-off across the full stack, ensuring power integrity and signal integrity targets are met.
Collaborate with the AIIS and Silicon Engineering teams to align power delivery and packaging solutions with product and silicon requirements.
Support thermal and integration reviews for current and future products.
Develop and maintain power-delivery methodology, flows, and design guidelines within the Custom Design toolchain.
Identify and mitigate single-point-of-failure risks in SI/PI workstreams; mentor and grow the team's packaging expertise.
Engage with external partners, substrate/interposer vendors, and OSAT houses to co-develop advanced packaging solutions.

Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field; PhD is a plus.
7+ years of experience in power delivery and/or advanced packaging design in a semiconductor or deep-tech environment.
Demonstrated expertise in on-die power grid design and package/PCB PDN analysis.
Hands-on experience with 2.5D and/or 3D IC packaging technologies, multi-chiplet integration, and interposer/substrate co-design.
Proficiency with industry-standard EDA tools for power integrity, PDN simulation, and package design.
Ability to work cross-functionally and communicate complex technical trade-offs to diverse stakeholder groups.
Strong written and spoken English communication skills.

Senior Advanced Packaging & Power Delivery Engineer

Key skills