Develop schematic symbols, CDFs, and callbacks
Develop device layout generators (PCELLs)
Develop as well as improve physical verification (DRC/LVS) rule decks
Develop rule decks for verifying Electrical Rule Checks (ERC)
Develop and validate Parasitic Extraction (PEX) technology files and flows
Develop and improve automated QA procedures to improve the efficiency and integrity of the design kits
Develop runsets for performing Layout vs Layout (LVL) and Schematic vs Schematic (SVS) checks
Enhancing and maintaining netlist generation procedures for internal/external analog circuit simulation tools
Work closely with the EDA software vendors to resolve tool bugs and drive new feature additions
Work closely with the design teams to understand their requirements and collaborate with device modeling, process development, and foundry groups to enable the efficient use of CAD tools and methodologies
Provide technical CAD support for ADI design community.

BS/MS in Electrical or Computer Engineering with an emphasis on IC design and semiconductor processes
Prior development experience and demonstrated understanding of CDFs, Callbacks, Layout P-cells, and schematic symbols
Demonstrated experience in development of DRC, LVS and Parasitic Extraction runsets
Proven skills in automation and programming languages (SKILL, Perl, Python, Tcl, Bash)
Understanding of analog/mixed signal simulation tools is preferred
Thorough understanding of physical verification (DRC/LVS) tools and methodologies
Knowledge of parasitic extraction tools from Siemens or Cadence
Familiarity with revision control systems and collaboration tools
Must possess excellent verbal and written communication skills
Must be detail-oriented, well organized, and a versatile team player.

Staff PDK Engineer

Key skills