About this role

Develop verification infrastructure (testbenches, BFMs, checkers, monitors, randoms)
Review and drive test plan execution for planned features
Ensure code and functional coverage of all RTL
Work with FPGA and software teams for testing
Plan for and be involved with post-silicon verification and debug

BS / MS or equivalent experience
5+ years of ASIC verification experience
Exposure to design and verification tools (VCS or equivalent)
Background with System Verilog and UVM methodology
Strong C/C++ programming experience
Prior Design or Verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5,6}, HBM, or GDDR)
Strong debugging and problem solving skills
Scripting knowledge (Python/Perl/shell)
Good interpersonal skills and ability to work in a team.

Senior Memory Controller Verification Engineer

Key skills