FPGA Digital Design Engineer (6+ month Contract)

Kepler Communications develops satellite connectivity and digital payload systems. The FPGA Digital Design Engineer will develop and implement FPGA designs for satellite payloads, including DSP or embedded-system functionality, and participate in the FPGA design flow from simulation through hardware testing.

Responsibilities:

• Develop custom IP for new features of the Kepler satellite digital payloads
• Iterate on current DSP and interface designs to improve reliability
• Work with IP core vendors to integrate new functionality into the Kepler designs
• Work with lead engineers in developing the communications and network architecture of our future satellite constellation
• Participate in conceptual design studies of new spacecraft

Requirements:

• Bachelor's Degree in Computer Engineering, Electrical Engineering or equivalent
• 5+ yr. working experience with FPGA/RTL design
• Verilog, SystemVerilog, or VHDL with the willingness to learn or pivot to SystemVerilog
• Xilinx FPGA(s). Specifically, Zynq and UltraScale
• Solid understanding of timing principles, including clock domain crossing and timing closure
• Strong scripting skills (e.g Python, Tcl, csh/bash, etc.)
• Experience with FPGA tools (e.g Vivado, Quartus), HDL Simulation Tools (ModelSim)
• Masters of Science in Computer/Electrical Engineering, or equivalent
• Experience in coherent digital demodulation of waveforms such as BPSK, QPSK, QAM
• Experience with memory mapped interfaces such as AXI, Wishbone, Avalon
• Experience with high-speed transceivers for protocols such as JESD204B, PCIe, SATA
• Experience with Linting tools, Questa Sim or Riviera-Pro
• Experience with Xilinx Versal and RFSoC
• Experience designing printed circuit boards
• Knowledge of radio-frequency electronics design