We are looking for an experienced RTL + SD Design Engineer with strong hands-on expertise in Verilog RTL development, memory subsystem design, synthesis, and standard-cell-based design implementation.
The ideal candidate should have experience working across RTL design and the downstream design flow, including synthesis, physical implementation, timing analysis, and design closure.
Architect and design memory subsystems for ASIC/SoC platforms.
Develop, implement, and debug synthesizable Verilog RTL code.
Perform synthesis and generate optimized gate-level netlists.
Work on standard-cell-based design implementation and optimization.
Perform place and route activities as required.
Drive design closure, including timing, DRC, LVS, and EM/IR.
Execute Static Timing Analysis (STA) and resolve timing violations.
Run and debug logical equivalence checks between RTL and synthesized netlists.
Develop Python automation scripts for design flows and engineering tasks.
Collaborate with cross-functional RTL, synthesis, and physical design teams.
Strong hands-on experience in RTL design and Verilog coding.
Experience with memory subsystem architecture and memory behavior.
Solid understanding of standard-cell-based ASIC design.
Hands-on experience with logic synthesis and gate-level netlists.
Experience with physical design, Place & Route, and design optimization.
Proficiency in STA, timing closure, DRC, LVS, and EM/IR.
Experience with Logical Equivalence Checking (LEC).
Strong Python programming and automation scripting skills.
Familiarity with industry-standard ASIC/EDA design tools.
Excellent communication, problem-solving, and collaboration skills.
Strong combination of RTL design and standard-cell design experience.
Ability to work independently across multiple stages of the ASIC design flow.
Self-motivated, technically strong, and comfortable handling multiple priorities.
Please submit candidates with strong hands-on RTL + SD experience, particularly in memory subsystem design and ASIC implementation.
