Senior Timing and Clocking Characterization Engineer (DLL / Duty-Cycle / STA)

Senior Timing and Clocking Characterization Engineer (DLL / Duty-Cycle / STA) 

Location: Mountain View, CA Area (Onsite/Hybrid) 

The Role 

You will own timing for custom clocking circuits: characterize them at the transistor level, turn the results into signoff-quality timing models, and make sure they close timing inside the full chip. The work sits at the boundary between analog circuit design and digital timing signoff. 

What you will do:

• Characterize custom and mixed-signal clocking blocks including DLLs, DCCs, digitally controlled delay lines, phase interpolators and clock dividers across PVT corners. 
• Build Liberty (.lib) timing models including timing arcs, setup/hold, minimum pulse width, NLDM/CCS and LVF. 
• Analyze delay, duty-cycle distortion, jitter contribution, lock range and delay resolution and correlate timing models against SPICE. 
• Write and validate SDC constraints including generated clocks, false paths and multicycle paths. 
• Run STA (PrimeTime or Tempus) at block and chip level and debug timing violations. 
• Support physical design handoff with ETMs and parasitic extraction (StarRC or Quantus). 
• Automate characterization and STA flows using Python, Tcl or Perl. 

Required

• BS or MS in Electrical Engineering with 7+ years in custom circuit timing, characterization or STA. 
• Hands-on characterization using Cadence Liberate/Liberate AMS, Synopsys PrimeLib/SiliconSmart, Synopsys NanoTime or equivalent SPICE-based flows. 
• Production STA experience with Synopsys PrimeTime or Cadence Tempus including MMMC and OCV/AOCV/POCV. 
• Working knowledge of DLLs, duty-cycle correction and delay-line circuits. 
• SPICE simulation with HSPICE, Spectre or PrimeSim/FineSim. 
• Strong scripting in Python, Tcl or Perl. 

Preferred

• Clocking for DDR, LPDDR, HBM memory PHYs, SerDes or die-to-die interfaces. 
• FinFET or gate-all-around process experience with two or more tapeouts. 
• Physical design exposure using Innovus, ICC2 or Fusion Compiler. 
• Characterizing circuits outside standard temperature ranges including cryogenic operation.