About this role

Title: DV Engineer - W2
Location: San Jose, CA and Austin, TX, Vancouver, Canada (Hybrid 3 days Onsite)
Duration: 12 months
Interview: MS Teams

Responsibilities:

Develop and implement comprehensive functional verification environments, including monitors, checkers, scoreboards, and assertions
Utilize expertise in AMBA bus protocols, ARM CPU, and optionally PCI Express and/or Ethernet bus protocols to ensure robust verification processes
Collaborate with cross-functional teams to integrate and troubleshoot verification components within the overall system
Employ scripting languages (PERL/Python/Shell/Makefile) for automation and efficiency in verification processes
Contribute to the overall success of the team by actively participating in debugging sessions, providing valuable insights, and maintaining effective communication within the team.

Requirements/Skills:

Strong System Verilog/UVM knowledge with practical experience on live projects
Expertise in AMBA bus protocols, ARM CPU, and experience in PCI Express and/or Ethernet bus protocols (desirable)
Proficiency in Unix, Configuration Management, Bug tracking, and verification dashboarding tools
Experience in developing functional verification environments, including components like monitors, checkers, scoreboards, and assertions, along with knowledge of verification methodologies using random stimulus and functional coverage.

DV Engineer

Key skills

About this role