Responsible for SoC level verification, driving verification execution, integration, coverage closure, low-power verification, GLS, and test-chip validation activities.
Key Responsibilities
1. Develop and execute SoC-level verification plans, testcases, and coverage models to validate subsystem interactions, system functionality, and integration requirements.
2. Integrate IPs, UVCs, and VIPs into the SoC verification environment.
3. Drive functional/code coverage closure, power-aware verification, and Gate-Level Simulations (GLS).
4. Perform debug of RTL, integration, protocol issues.
5. RAL Modeling and verification.
6. Own test-chip verification and collaborate with Design, DFT, Firmware, and Architecture teams for verification signoff.
Skill Requirements
1. Strong expertise in SystemVerilog, UVM, and SoC verification methodologies.
2. Experience in testbench bring-up, SoC integration, and coverage-driven verification.
3. Hands-on experience in RAL modeling and RAL-based register verification, including register access, mirroring, prediction, and functional coverage.
4. Hands-on experience with UPF-based low-power verification and GLS debugging.
5. Knowledge of JTAG, DAC, and analog/mixed-signal model verification.
6. Strong debugging, automation, and stakeholder management skills
