Senior DFT Engineer

K2 Space Corporation builds high-power satellite platforms for commercial and government missions across multiple orbits. The company is seeking a Senior Design-for-Test Engineer to lead DFT architecture and implementation for complex mixed-signal SoCs, including test strategy, ATPG, verification, signoff, and silicon debug.

Responsibilities:

• Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan
• Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies
• Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation
• Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions
• Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.)
• Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation
• Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior
• Contribute to methodology development, automation, and flow improvements

Requirements:

• B.S. or M.S. in Electrical Engineering or related field
• 7+ years of experience in DFT for complex SoCs
• Strong hands-on experience with RTL DFT insertion (scan, compression, test points), and ATPG tools and flows
• Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies
• Experience with low-power DFT techniques
• Familiarity with mixed-signal integration challenges and test methodologies
• Strong debugging skills across RTL, gate-level, and silicon
• The person hired for this role must therefore either be a “U.S. person” as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license
• Experience with MBIST/LBIST implementation and memory repair flows
• Knowledge of IEEE 1149.x (JTAG/boundary scan) standards
• Experience with multi-voltage domain and power-aware DFT
• Exposure to physical design impacts on DFT (scan chain reordering, congestion, timing)
• Scripting experience for automation
• Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs
• Prior involvement in A0 silicon bring-up and yield ramp
• Experience working in cross-functional, geographically distributed teams