ASIC Verification Engineer Job Details | Capgemini

Capgemini is a global leader in engineering services, and they are seeking an ASIC Verification Engineer to join their team. The role involves ensuring the quality of designs and developing verification processes for ARM-related IPs throughout the project lifecycle.

Responsibilities:

• Assure the overall quality of our designs, contributing to exciting launches of wireless portable hardware
• Maintain a strong focus on ARM IPs (CPU — Cortex‑A v9 architecture, GPU — Mali, Debug — CSS600, CoreSight, etc.), where your expertise will enable architectural/design reviews and rapid ramp‑up on verification of these blocks
• Serve as an individual contributor, owning and developing the verification of our core IP blocks
• Take ownership throughout the entire project lifecycle, including: specification reviews, verification plans, test case development, UVM environments, coverage (analysis), debugging, GLS, etc
• Work closely with other teams to gather relevant information and share design insights to improve requirements and specifications, while also providing critical support in their debugging efforts
• Collaborate with the global verification team to enhance processes and lead initiatives that improve design quality and strengthen verification methodologies to build a best‑in‑class verification team

Requirements:

• Proven (5+ years) hands‑on experience with state‑of‑the‑art verification methodologies and processes, including UVM/SystemVerilog, formal verification, constraint‑random verification, assertions, coverage metrics, coverage analysis, gate‑level simulation, key performance indicators testing, etc
• Strong understanding of ARM‑related IPs is required: CPU (Cortex‑A v9 architecture), GPU (Mali), Debug (CSS600, CoreSight), etc
• Hands‑on experience designing and implementing C‑based test cases to configure and test ARM IPs, along with the ability to reuse manufacturer‑provided test benches
• Experience using and creating a UVM‑based test environment for block‑level verification, and reusing those environments at subsystem level
• Ability to read and understand RTL code (SystemVerilog, Verilog, VHDL)
• Experience with revision control systems and CI/CD techniques
• Strong interpersonal skills with the ability to collaborate across teams and work independently
• Excellent process development, documentation, and written and verbal communication skills