Lead ASIC DFT Engineer

InfoStride is seeking a Lead ASIC DFT Engineer with extensive experience in Design-for-Test for complex ASIC and SoC designs. The role involves leading DFT architecture, implementation, verification, and cross-functional debug efforts.

Responsibilities:

• Lead DFT architecture, implementation, verification, ATPG pattern generation, fault coverage closure, silicon bring-up, and cross-functional debug efforts

Requirements:

• 10+ Years in ASIC DFT Engineering
• Strong expertise in Scan, ATPG, MBIST/LBIST, JTAG, Boundary Scan, Timing Simulations, SDF, SDC, Silicon Debug, and Post-Silicon Validation
• Experience with Synopsys DFTMax, TetraMAX, Tessent, SSN, Pattern Retargeting/Porting, Diagnosis, and DFT Sign-off
• Leading DFT architecture, implementation, verification, ATPG pattern generation, fault coverage closure, silicon bring-up, and cross-functional debug efforts
• Strong scripting skills in TCL, Perl, or Python
• Experience with large SoC designs