FortifyIQ is seeking a Verification Engineer to contribute to the validation of advanced chip designs. The role involves creating and maintaining UVM environments, writing tests, and ensuring functional coverage for high-performance silicon products through collaboration across architecture, design, and circuit teams.
Responsibilities:
- Understand chip and subsystem architecture
- Develop, maintain, and extend UVM-based verification environments
- Write test plans, test cases, and sequences for block- and chip-level verification
- Debug design issues based on architectural specifications
- Work with design and architecture teams to meet quality and schedule goals