Distinguished Engineer, Digital ASIC

Butterfly Network, Inc. is driving a digital revolution in ultrasound imaging with its proprietary technology and software solutions. They are seeking a Distinguished Engineer to lead digital IC/ASIC design efforts, focusing on complex digital architectures and integration with cross-functional teams.

Responsibilities:

• Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs
• Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design
• Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces
• Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design
• Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP
• Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff
• Comfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts)
• Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths)
• Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures
• Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs

Requirements:

• BS/MS/PhD in EE/CE/CS or equivalent practical tapeout experience
• 8–12+ years (typical Principal level) in digital IC / ASIC / SoC design with significant hands-on RTL ownership
• Strong understanding of digital IC implementation at the silicon level, including timing closure implications, clock/reset domain architecture, power-aware design, and PPA (power, performance, area) tradeoffs
• Proven ability to own complex digital IC subsystems from architecture and PPA tradeoffs through RTL implementation, verification signoff, and tapeout handoff to physical design
• Strong RTL skills in SystemVerilog/Verilog to implement silicon-proven digital architectures, including pipelined datapaths, control logic, state machines, and high-throughput streaming interfaces
• Experience architecting sustained high-throughput digital datapaths, including buffering, arbitration, backpressure, bandwidth budgeting, and SRAM/memory hierarchy design
• Prior work at advanced technology nodes (28nm or smaller), including timing closure challenges and integration of third-party IP
• Experience collaborating with verification teams to validate complex digital architectures and resolve functional issues through tapeout signoff
• Comfortable working cross-functionally with analog, systems, and packaging/board teams to close chip-level requirements and integration details, including hardware–firmware interfaces (register maps, control/status paths, data-plane contracts)
• Experience implementing compute-intensive digital pipelines (e.g., DSP, beamforming, AI, or MAC-heavy/vector datapaths)
• Exposure to medical imaging / ultrasound systems, beamforming pipelines, or sensor data acquisition architectures
• Experience designing or integrating programmable digital compute blocks (e.g., AI accelerators, MPUs, or eFPGA fabrics), including instruction/control interfaces, memory hierarchy, data movement, and PPA tradeoffs