About this role
Role Overview
- Set multi-generation, cross-portfolio Memory interface strategy.
- Drive performance-versus-power analysis that influences major silicon trade-offs and product roadmap decisions.
- Lead silicon and vendor/IP co-architecture.
Requirements
- MSEE, MSCE, or PhD or equivalent experience demonstrating significant impact in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 18+ years of relevant industry and/or academic experience.
Benefits
- equity
- benefits