Participate in design and responsible for verifying complete IP macros specifically applicable for Mythic product architecture utilizing the available licensed NVM technologies from foundries
Involve in NVM architecture for optimum performance and area of Analog Compute Engine
Design and verify the new circuits to handshake with the analog computation and the digital controlling blocks
Design, optimize and verify the NVM circuits and functional blocks (including and not limited to high voltage generator block, x-path, y-path, test and peripheral circuits) at the full chip level
Responsible for NVM full chip circuit simulation setup, debugging, and verification
Responsible for RNM and functional model of NVM circuits for verification
Participate in RNM and functional model of NVM circuits for computational software
Work closely with the validation engineers to expedite the silicon evaluation process and backend teams for the production qualification releases
Requirements
Hands-on experience in NVM embedded or NVM product design, verification and production
Hands-on experience in NVM full chip circuit simulation setup, debugging, and verification
Hands-on experience modeling circuits using Python, Verilog-A, and System Verilog Real Number Modeling
Familiar and hands-on experience some or all memory circuit block design: decoder, high voltage switches, charge pumps, HV and LV regulator, bandgap, high performance low power sense amp, monitoring, and BIST capability
Good understanding & knowledge of semiconductor device physics, and advanced process technology