Develop and execute comprehensive verification plans for mixed signal logic components to ensure alignment with microarchitecture specifications.
Design and implement test benches and verification environments using advanced methodologies such as OVM and UVM.
Perform system-level simulation to verify functionality, analyze power and timing, and identify potential design issues.
Collaborate with digital and analog architects, RTL developers, and physical design teams to optimize verification strategies and meet performance, power, and functional goals.
Debug presilicon issues by replicating, root causing, and implementing corrective measures for failing tests.
Create and maintain analog behavioral models and contribute to the development of reusable verification infrastructure and methodologies.
Document test plans, verification results, and drive technical reviews with design and architecture teams.

A Bachelor's or BS degree and/or equivalent knowledge in a specialized field, with at least 3 years of relevant experience, OR
A Master's degree and/or equivalent knowledge in a specialized field, with at least 2 years of relevant experience, OR
PhD and/or equivalent knowledge in a specialized field, with at least 1 year of relevant experience
Experience with verification methodologies such as OVM and UVM.
System Verilog and Verilog for test environment and design verification.
Developing test environments for functional verification of mixed signal logic components.

Mixed Signal IP Verification Engineer

About this role