Lead cross-functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design Rules, DTP, and CAD to define and continuously enhance DFM rules that accelerate yield improvement and technology ramp on advanced logic nodes
Translate silicon learning and yield insights into actionable feedback for design teams, enabling timely updates to layout and DTCO methodologies and flows that catch yield issues earlier in the design cycle
Develop, refine, and optimize yield tools and flows within the foundry environment, supporting inline yield detection and continuous process optimization
Define and evolve DFM methodologies by deeply understanding silicon process flows, predicting layout and design marginalities, and collaborating with cross-functional partners to develop robust mitigation rules
Drive scribe line layout design and process monitoring structure development to support advanced node characterization and manufacturing readiness
Manage design rule development, validation, and waiver processes, ensuring alignment between manufacturing constraints and customer design requirements
Support foundry customers across multiple market segments by developing and implementing tailored DFM solutions that meet diverse application requirements

Master’s in Electrical Engineering, Physics, or a closely related field
6+ years of experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environment
Experience in DTCO methodologies, including SRAM and Standard Cell design
Experience leading cross-functional teams in defining derivative architectures encompassing design rules, transistors, and interconnects
Hands-on experience in advanced node test chip design and scribe line optimization across 3nm–16nm FinFET or sub-3nm GAA FET technologies, including Backside Power Delivery (BSPD)

Senior Staff Collateral Design and DFM Engineer

Key skills