About this role

develop logic design, register transfer level (RTL) coding, and simulation for SoC designs
integrate IP blocks and subsystems into full chip SoC or discrete component designs
participate in defining architecture and microarchitecture features
perform quality checks across various logic design aspects from RTL to timing/power convergence
apply strategies, tools, and methods to write RTL and optimize logic
ensure design integrity for physical implementation
work closely with verification teams, review verification plans and resolve failing RTL tests
follow secure development practices and collaborate with IP providers

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
4+ years of experience in RTL design and implementation for ASIC/SoC development
Proficiency in Verilog/System Verilog for RTL coding and design
Experience with synthesis tools and timing closure methodologies
Understanding of clock domain crossings, power optimization, and timing closure
Exposure to SoC system integration and CPU subsystem design
Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
Knowledge of high-speed and low-power design techniques
Experience with static timing analysis (STA) tools and methodologies
Hands-on experience with formal verification tools and techniques
Basic scripting skills (Python, TCL, etc.) for automation

Design Engineer – AI SoC Development

Key skills