Key skills
C++CWorkdayCollaboration
About this role
Role Overview
- Acquire knowledge of the architecture and microarchitecture of the ASIC
- Participate in defining overall verification strategies and methodologies
- Develop, maintain, and publish verification specifications
- Define test plans in close collaboration with the logical design team
- Develop verification environments, test cases, and coverage models using UVM / SystemVerilog / C++
- Track, analyze, and debug simulation errors
- Monitor and analyze simulation coverage results
Requirements
- 3–5 years of experience
- Bachelor’s Degree (BE / BTech) or Master’s Degree (ME / MTech)
- Experience using constraint-random, coverage-driven functional verification methodologies under the UVM verification framework
- Mastery of UVM or equivalent verification methodologies
- Profound knowledge of simulation and coverage analysis tools
- Strong problem-solving skills
- Participation in the successful verification of a complex SoC or ASIC
- Ability to work professionally in English and Spanish
Benefits
- Flexible Work Schedule
- Half day Fridays
- Intensive summer workday