Perform low-level and complex debug across multiple systems, subsystems, or SoC levels for Intel products.
Develop validation plans and execute tests for multiple domain
and system-level features/flows in the SoC.
Develop and implement techniques for faster SoC and platform-level debug while isolating failing system components.
Utilize design-for-debug (DFD) tools and scripts to continuously improve debug discipline.
Conduct root cause analysis, resolve triage failures and marginality issues, and track SoC debug progress.
Collaborate with design, system validation teams, and high-volume manufacturing factories to characterize new device features and functionalities.

Bachelor’s degree in electrical engineering, computer Engineering, computer science or related technical discipline with 1+ years or Masters electrical engineering, computer Engineering, computer science with experience in SoC design and debug or equivalent experience
6+ months of experience with the following technical skills: Proficiency in SoC design, architecture, and debug techniques, including DFD tools and methodologies
Strong understanding of firmware and software integration in hardware systems
Ability to apply debug workflows using advanced test methodologies and failure isolation techniques.
Preferred Qualifications: Master’s degree in electrical engineering, Computer Engineering, or related disciplines
Exposure to collaborating across design and validation teams to achieve debug readiness
Familiarity with Graphics and Power Management flows in an SoC design
Drive to influence technical strategies and align organizational goals with technical vision

Post-Silicon Validation and Debug Engineer

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