Own the SoC and Product Specification stack for a 1.6T retimer SoC and the AEC product it enables, at 224G/lane PAM4
Author and maintain normative specifications (SHALL/MUST/SHOULD/MAY language with REQ-ID traceability) that RTL, firmware, software, SI/PI, manufacturing, qualification, and customer engineering teams execute against
Represent architecture in hyperscaler and strategic platform customer specification negotiation, including qualification test point, FEC telemetry, CMIS vendor-page, and thermal envelope commitments

12+ years in shipping high-speed interconnect (retimer, gearbox, PHY, AEC, AOC, coherent optics, SerDes-centric networking silicon)
Prior System Architect, Chief Architect, or Principal Systems Engineer role on a shipping 100G/lane or higher product
Direct authorship of at least one product spec and one silicon spec on a shipping product
PAM4 link training, FEC, and on-die telemetry fluency at the specification level
DOORS / JAMA / equivalent traceability tooling

System Architect

Key skills