Drive chip-package-system co-design for optimal power delivery and decoupling strategies.
Lead power integrity architecture and implementation for advanced chiplet-based products and heterogeneous integration platforms.
Develop PI design guidelines, methodologies, and signoff criteria for high-current designs.
Analyze and optimize high-current delivery paths for AI/HPC workloads based on Powerlattice chiplets.
Define and optimize end-to-end PDN solutions across: Die, Package, Interposer and PCB/system

8+ years of experience in power integrity and/or signal integrity for high-performance SoCs.
Exceptional proficiency in power integrity or signal integrity tool chain and simulation flow.
Hands-on experience extracting, building, and validating SoC package electrical models.
Strong experience with package-level PI/SI, including substrates, interposers, and advanced packaging (2.5D / 3D).
Deep proficiency with PI/SI simulation tools and analysis workflows.
Strong debugging skills across simulation and electrical testing environments.
High level of professionalism, discretion, and technical judgment.
Comfortable working independently and proactively solving problems.
Working experience at major processor or ASIC companies in the related technical area.
Proven experience as engineering or project lead in a related technical area.
Hands-on experience with electrical test methodologies and instrumentation for power integrity or signal integrity.

Staff/Senior Staff Power Integrity Engineer – Power Delivery

Key skills