Define the ECU verification architecture: Build the end-to-end verification concept covering component, subsystem, and system levels, including entry/exit criteria and quality metrics
Own requirements traceability and coverage: Ensure bidirectional traceability from system requirements to design artifacts and verification evidence; define and track coverage (functional, interface, diagnostic, and safety-related)
Specify verification environments and tooling: Define test environment architecture, logging/trace strategy, fault injection approach, and tool qualification expectations; align on reusable frameworks and standards across programs
Drive cross-functional technical alignment: Work with HW, embedded SW, system architects, and validation leads to ensure designs are verifiable (DFV), interfaces are testable, and assumptions are reviewed and documented
Lead verification planning for customer programs: Translate OEM/Tier 1 needs into verification requirements and deliverables; support technical reviews and audits with clear evidence packages
Own risk management and escalation: Identify verification gaps and high-risk features; propose mitigation plans and drive execution across teams