Key skills
PythonCommunicationCollaboration
About this role
Role Overview
- Define and implement chip-level and block-level DFT strategies for complex ASICs
- Develop and integrate scan architecture, compression logic, boundary scan, MBIST, and LBIST solutions
- Drive ATPG generation, fault simulation, diagnosis, and coverage closure
- Collaborate with RTL, verification, physical design, and test engineering teams
- Support synthesis, STA, and physical design flows with DFT based constraints
- Perform DFT verification using simulation
- Lead silicon bring-up, debug and failure diagnosis activities
- Develop automation scripts and methodologies to improve DFT productivity and quality
Requirements
- Bachelor's, Master’s or PhD degree in Electrical Engineering or related discipline and proven industry experience in a DFT position
- Strong understanding of digital design and test methodologies
- Hands-on experience with:
- Scan insertion and scan compression
- ATPG and fault simulation
- MBIST/LBIST implementation
- JTAG / IEEE 1149.1 standards
- Test coverage analysis and diagnosis.
- Experience with industry-standard EDA tools such as:
- Siemens Tessent
- Synopsys TetraMAX / TestMAX
- Strong scripting skills in Tcl & Python
- Familiarity with Verilog/SystemVerilog and simulation environments
- Excellent debugging and problem-solving skills
- Good communication and excellent collaboration skills.
Tech Stack
- Python
Benefits
- Inclusion and fairness
- Meaningful community engagement
- Enjoyable employee experiences