Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design specifications are met.
Develop IP verification plans, test benches, and verification environments to ensure comprehensive coverage of mixed signal microarchitecture specifications.
Execute detailed verification plans, define and run system simulation models, analyze power and timing, and uncover bugs to optimize design functionality.
Debug issues in the presilicon environment through replication, root cause analysis, and implementation of corrective measures to resolve failing tests.
Collaborate with digital and analog architects, RTL developers, and physical design teams to enhance the verification of complex architectural and microarchitectural features.
Drive technical reviews of test plans and proofs with design and architecture teams, documenting all processes and findings.
Maintain and continually improve functional verification infrastructure, methodologies, and tools to align with evolving industry standards.

Bachelor's or Master's degree in Electronics, VLSI Engineering, or a related field.
4+ years of experience with a Bachelor's degree, or 3+ years of experience with a Master's degree in ASIC/SoC verification.
Proficiency in System Verilog, UVM, and Verilog for mixed signal verification.
Experience with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa.
Strong scripting skills in Python, Perl, or Tcl for testbench automation.
Knowledge of standard protocols including JTAG/IJTAG/CRI/APB, and multi-clock domain mixed signal designs.
Expertise in constraint-random test generation, root cause analysis, and debugging of complex mixed signal designs.

Mixed Signal Design Verification Engineer

Key skills