Performs functional logic verification of an integrated SoC to ensure design will meet specifications
Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications
Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs
Replicates, root causes, and debugs issues in the presilicon environment
Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams

Bachelor's degree in Electrical Engineering, Computer Science, or a related field with 6 or more years of industry experience
Master's degree in Electrical Engineering, Computer Science, or a related field with 4 or more years of industry experience
PhD in Electrical Engineering, Computer Science, or a related field with 2 or more years of industry experience
6+ years experience in OVM/UVM methodologies and System Verilog-based constrained random verification
Developing and executing verification test plans, including debugging and coverage closure
Scripting languages to facilitate automation

SOC Design Verification Engineer

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