Key skills
Perl
About this role
Role Overview
- Support the adoption of Cadence Products for Chip Designer Customers
- Articulate design methodologies involving Cadence tools
- Own block implementation, top-level implementation and Signoff focused efforts
- Involve in competitive benchmarking on complex blocks including CPUs, GPUs and DSP cores
- Assist customers with adopting Cadence Front End tools in Synthesis with Genus DFT & Scan with Encounter Test
- Drive best practices and lessons learnt from evaluations/benchmarks back into product development
Requirements
- Design experience in ASIC using industry-standard hardware description languages (Verilog)
- 7+ years experience and strong technical knowledge of Cadence products
- Experience with Place and Route tools (Physical Synthesis, PnR, CTS, Static Timing Analysis)
- Innovate with Low Power and Multi-Voltage Design Techniques
- Experience supporting RTL-to-GDS implementation flows using Encounter Digital Implementation Platform
- Ability to manage strategic customer evaluations/benchmarks
- Create and conduct technical presentations and product demonstrations
- Some TCL/Perl Scripting for quick Design Automation solutions
Tech Stack
- Perl
Benefits
- Equal Employment Opportunity Policy
- Privacy Policy for Job Applicants
- E-Verify participation in certain U.S. locations