develop logic design, register transfer level (RTL) coding, and simulation for SoC designs while integrating IP blocks and subsystems into full chip SoC or discrete component designs
participate in defining architecture and microarchitecture features of the blocks being designed
perform quality checks across various logic design aspects ranging from RTL to timing/power convergence
apply various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation
review verification plans and implementation to ensure design features are verified correctly
address security threat models and security objectives within the design
collaborate with verification teams to ensure comprehensive coverage and robust validation of all design aspects
mentor junior engineers and contribute to best practices for design methodology and quality

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
7+ years of experience in RTL design and implementation for ASIC/SoC development
Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure
Hands-on experience with SoC system integration and multicore CPU subsystem design
Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
Expertise in high-speed and low-power design techniques
Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization
Familiarity with industry standard EDA tools, including simulators (VCS, Questa, Xcelium), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II)

Lead Senior Design Engineer – AI SoC Development

Key skills