Provide comprehensive technical support on layout verification and parasitic extraction challenges
Collaborate with internal teams and external stakeholders on physical and layout design rules and extraction issue resolution
Deliver customer-facing technical support with a focus on physical verification challenges and solutions
Create application notes, comprehensive documentation, and deliver training presentations to customers
Lead optimization of physical verification flows for advanced CMOS processes (22nm and below)

US Citizenship required
Ability to obtain a US Government Security Clearance
Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study
3+ years of experience with advanced CMOS processes (22nm and below)
3+ years of combined experience in layout verification and parasitic extraction EDA tools
3+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting)

Competitive compensation
Access to Intel's most advanced foundry technologies and verification tool suites
Professional development in physical verification methodologies and foundry services
Direct impact on national security through advanced semiconductor verification solutions

Physical Verification Engineer

Key skills