Verification Engineer – G3, SoC Simulation, Functional Verification

Role Overview

• Define and implement SoC verification strategies
• Lead development of verification environments
• Drive end-to-end SoC verification
• Develop and maintain test plans and cases
• Analyze failures and debug root causes
• Mentor junior engineers

Requirements

• 6+ years of experience in SoC verification
• Experience with UVM/SystemVerilog
• Knowledge of SoC protocols (AXI, AHB, APB, PCIe, USB, Ethernet)
• Exposure to emulation platforms (Palladium, Veloce, ZeBu, etc.)

Benefits

• Career Development Opportunities
• Commitment to sustainability and inclusivity