Join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols
Responsible for the verification of digital RTL and development of re-usable verification components and environments
Contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure
Communicate with all members of the technical staff regarding overall project development progress and status
Work as part of a small and focused team of engineers and collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies
Requirements
Bachelor of Science in Electrical(EE)/Computer Engineering (CPE) or Computer Science (CSC)
Understanding of verification architecture and methodologies
Understanding of Metric Driven Verification
Understanding of Universal Verification Methodologies
Understanding of the identification, planning and creation of functional coverage and checks
Understanding of System Verilog Assertions (SVAs)
Understanding of digital design flow
Master of Science in EE/CPE/CSC (preferred)
Experience with SystemVerilog UVM coding language (desired)
Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk (strongly preferred)
Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
Exposure to Formal Verification Technologies
Exposure to Mixed Signal Design experience
Experience with Cadence tools
Exposure to Low Power verification experience using CPF or UPF
Tech Stack
Perl
Python
Ruby
Benefits
Paid vacation and holidays
Leave of absence programs
Registered Retirement Savings Plan (RRSP)
Tax Free Savings (TFSA) plan for post-tax investment savings
Employee Stock Purchase Plan
Group health coverage that includes dental, vision and Emotional Wellbeing Support (EAP) benefits for you and your eligible dependents