Top-down SoC Floorplan activities like best IP placement for latency/area in collaboration with architects, partitioning, PG grid creation, multi-power domain planning, pin-cutting, bump-planning by working with package/platform.
Estimate die-area and define optimal physical dimensions for SoC by including product costs like die-per-reticle, right technology selection/metal stack and reuse from different product family.
Drive execution and supervise progress of smaller blocks or sub-systems influencing their physical placement, shape, and channel planning to help them achieve best area and convergence schedule.
Plan short and long-term work schedule, understanding dependencies between different domains like top, block place and route.
Collaborate with other stake holders like the clock design to deliver the physical block level floorplans for APR and with the power delivery team on tradeoffs for metal allocation for signal and power.
Help drive methodologies, tools and best-known methods to streamline Floorplan Physical Design work to achieve best-in-class on schedule delivery.

Bachelor in Electrical/Electronics/Computer Engineering with 3+ years of relevant experience or Master's degree in Electrical/Electronics/Computer Engineering with 2+ years of relevant experience.
2+ years of experience using industry-standard EDA tools for floorplanning and APR.
1+ years of experience with multi-power domain designs.
1+ years of experience with Synopsys Fusion Compiler.
3+ years of experience with TCL, Python or Perl programming.
2+ years of experience with Calibre or ICV verification.

Fullchip Floorplan Design Engineer

Key skills