You are a key contributor for the top-level floorplan, driving block-level floor-planning and execution
You execute and deliver key floor-planning activities (placement, shaping, pinning, methodology) with production-grade quality
You drive the critical PPA aspects of floor-planning by collaborating with the Architecture, RTL, PPA, and Physical Design teams
You work with the CAD team to continuously improve the floor-planning design methodology
You lead the physical-verification convergence of the top-level floorplan to achieve final GDS delivery
Requirements
5+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 3+ years of experience with a Master’s degree, or 1+ years of experience with a PhD
Skilled in EDA flows and methodologies and industry standards pertaining to Floor-planning
Highly proficient in Top and Block level Floor-planning techniques including partitioning, pinning, and budgeting
Experience with power-grid implementation and clock distribution
Strong scripting and automation skills in Python, TCL, Shell, or Perl
Hands on experience in delivering final GDS for high-performance IPs and SOCs