Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications.
Design and implement simulation environments and testbenches to validate FPGA functionality and performance.
Create and run functional and directed/random test scenarios to ensure comprehensive design coverage.
Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage.
Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle.
Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality.
Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals.

Must have 7-14 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans – at block, sub-chip and chip levels.
Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform-based debugging tools.
Exposure to UVM (or similar) verification methodologies is required.
Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred.
Should be conversant with technologies like the Ethernet, PCIe, I2C, SPI etc. Knowledge of telecom protocol is preferred.
Structured and thorough with analytical and troubleshooting skills.
Good written and oral communication skills are required.
Flexible, innovative, self-driven and willing to take initiatives.
Highly motivated team player with exceptional leadership capability.

Staff FPGA Verification Engineer

Key skills